Conventionally, an A/D converter used in an image sensor and the like is generally configured to perform A/D conversion by a single slope A/D conversion system and the like and includes a counter circuit. In such counter circuit, current does not flow when a count value is not inverted, but the current flows when the count value is inverted, so that noise might be generated due to power source variation. Especially, simultaneous inversion of the count values (inversion of all bits) might cause large power source variation.
Therefore, a method of preventing such simultaneous inversion is considered. For example, a system of dividing operation timings of counters into former counts and latter counts is considered (for example, refer to Patent Documents 1 and 2). Also, operation in which positive and negative edges are used such that the A/D conversion may be performed with shifted count timings is considered (for example, refer to Patent Document 3).